A Set of Novel Multiplexer-Based Architectures for Full Adder Designs

In this paper, five new multiplexer-based architectures for 1 -bit full adder circuit designs are proposed. Following these architectures, various full adder circuits can be built through different circuit implementations of multiplexers. For instance, in this paper, we demonstrate that by substituting each multiplexer with two transmission gates, a set of new full adder circuits are ready to be obtained. These new adder circuits along with the conventional 28-transistor CMOS adder are tested vigorously using HSPICE under various frequency and loading conditions. Testing result shows that the new adders are 19.9% faster than the conventional 28-transistor CMOS adder and Power-Delay product is reduced by up to 18.4%, making these new adder circuits good primitive leaf cells in high performance VLSI designs. Key-Words: Architecture, full Adder, high performance, Multiplexer, transmission gate, VLSI circuit